library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ProcesseurEtCo is
  Port ( CLK         : in  STD_LOGIC;
	 RESET       : in  STD_LOGIC;
	 HS,VS,R,G,B : out STD_LOGIC;
	 PIN         : in  std_logic_vector(3 downto 0);
	 POUT        : out  std_logic_vector(7 downto 0));
end ProcesseurEtCo;

architecture Behavioral of ProcesseurEtCo is

  component processeur is
    Port (
      CLK      : in  STD_LOGIC;
      RESET    : in  STD_LOGIC;
      ADPROG   : out  STD_LOGIC_VECTOR (15 downto 0);
      DPROG    : in  STD_LOGIC_VECTOR (15 downto 0);

      ADDATA   : out  STD_LOGIC_VECTOR (15 downto 0);
      DDATAIN  : in  STD_LOGIC_VECTOR (15 downto 0);
      DDATAOUT : out  STD_LOGIC_VECTOR (15 downto 0);
      WE       : out  STD_LOGIC;
      CE       : out  STD_LOGIC;
      OE       : out  STD_LOGIC;
      
      PIN      : in  STD_LOGIC_VECTOR (3 downto 0);
      POUT     : out  STD_LOGIC_VECTOR (7 downto 0)
      );
  end component;

  component ROMPROG
    Port (
      AD      : in  std_logic_vector (12 downto 0);
      DO    : out  std_logic_vector (15 downto 0);
      CLK      : in STD_LOGIC
      );
  end component;

  signal ADPROG,DPROG: std_logic_vector(15 downto 0);

  signal ADDATA    :  STD_LOGIC_VECTOR (15 downto 0);
  signal DDATAIN   :  STD_LOGIC_VECTOR (15 downto 0);
  signal DDATAOUT  :  STD_LOGIC_VECTOR (15 downto 0);
  signal WE        :  STD_LOGIC;
  signal CE        :  STD_LOGIC;
  signal OE        :  STD_LOGIC;

  component RAMDoublePort
    Port ( AD1   : in  std_logic_vector (12 downto 0);
           AD2   : in  std_logic_vector (12 downto 0);
           DIN1  : in  std_logic_vector (15 downto 0);
           DOUT1 : out  std_logic_vector (15 downto 0);
           WE1   : in  STD_LOGIC;
	   DOUT2 : out  std_logic_vector (15 downto 0);
           OE1   : in  STD_LOGIC;
           CE1   : in  STD_LOGIC;
	   RESET : in STD_LOGIC;
	   CLK   : in STD_LOGIC);
  end component;
  component VGA_lecture_memoire
    Port ( CLK   : in  STD_LOGIC;
           RST   : in  STD_LOGIC;
	   AD    : out std_logic_vector(12 downto 0);
	   D     : in std_logic_vector(15 downto 0);
           R     : out  STD_LOGIC;
           G     : out  STD_LOGIC;
           B     : out  STD_LOGIC;
           HS    : out  STD_LOGIC;
           VS    : out  STD_LOGIC);
  end component;


  signal ADVGA : std_logic_vector(12 downto 0);
  signal DVGA   :  STD_LOGIC_VECTOR (15 downto 0);
signal PINi : std_logic_vector(3 downto 0);
signal POUTi : std_logic_vector(7 downto 0);
begin
  PINi <= PIN;
  POUT <= POUTi;
  C_proc: processeur
    port map(
      CLK      => CLK             ,
      RESET    => RESET    ,
      ADPROG   => ADPROG   ,
      DPROG    => DPROG    ,

      ADDATA   => ADDATA   ,
      DDATAIN  => DDATAIN  ,
      DDATAOUT => DDATAOUT ,
      WE       => WE       ,
      CE       => CE       ,
      OE       => OE       ,

      PIN      => PINi      ,
      POUT     => POUTi     
      );

  C_rom: ROMPROG
    port map(
      CLK   => CLK, 
      AD   => ADPROG(12 downto 0) ,
      DO => DPROG
      );
  
  C_VGA     : VGA_lecture_memoire
    port map(
      CLK   =>CLK,
      RST   =>RESET,
      AD    =>ADVGA,
      D     =>DVGA,
      R     =>R,
      G     =>G,
      B     =>B,
      HS    =>HS,
      VS    =>VS
      );
  

  
  C_RAM     : RAMDoublePort
    port map(
      AD1   =>ADDATA(12 downto 0),
      DIN1  =>DDATAOUT,
      DOUT1 =>DDATAIN,
      CE1   =>CE,
      WE1   =>WE,
      OE1   =>OE,
      RESET =>RESET,
      CLK   =>CLK,
      AD2   =>ADVGA,
      DOUT2=>DVGA
      );

end Behavioral;

